The present invention relates to data processing apparatus and, more in particular, to memory apparatus for increasing the data processing rate.
Data processing rates continually increase due to advances made at both logic and the architectural levels of the processing system. Whether considering main memory or cache storage, these advances create an ever increasing demand for higher memory throughput, in other words, memory bandwidths. To satisfy this demand, storage space, for example, has been divided into independent, interleaved modules so that in one memory cycle, the memory system has the potential to service as many requests (i.e., addresses) as there are modules.
Memory components are a key substream in computer systems and represent a major hardware cost of the system. Large scale integration may be used to reduce memory component cost. However, two of the major concerns in designing efficient large scale integration memory systems are power consumption and input/output pin limitations. For a more detailed discussion of multiaccess memory, reference may be made to U.S. Pat. No. 4,104,719.